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CS5341
105 dB, 192 kHz, Multi-Bit Audio A/D Converter
Features
Advanced Multi-bit Delta-Sigma Architecture 24-bit Conversion Supports All Audio Sample Rates Including 192 kHz 105 dB Dynamic Range at 5 V -98 dB THD+N 90 mW Power Consumption High-Pass Filter to Remove DC Offsets Analog/Digital Core Supplies from 3.3 V to 5 V Supports Logic Levels between 1.8 V and 5 V Auto-Detect Mode Selection in Slave Mode Auto-Detect MCLK Divider
General Description
The CS5341 is a complete analog-to-digital converter for digital audio systems. It performs sampling, analogto-digital conversion, and anti-alias filtering, generating 24-bit values for both left and right inputs in serial form at sample rates up to 200 kHz per channel. The CS5341 uses a 5th-order, multi-bit Delta-Sigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. The CS5341 is available in a 16-pin TSSOP package for Commercial (-10 to +70 C) and Automotive grades (-40 to +85 C). The CDB5341 Customer Demonstration Board is also available for device evaluation and implementation suggestions. Please refer to "Ordering Information" on page 22 for complete ordering information. The CS5341 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as set-top boxes, DVD-karaoke players, DVD recorders, A/V receivers, and automotive applications.
VA 3.3 V to 5 V
VD 3.3 V to 5 V
VL 1.8 V to 5 V
Single-Ended Analog Input
AINL
Switch-Cap ADC High-Pass Filter
Low-Latency Digital Filters
Auto-detect MCLK Divider
Master Clock
FILT+
Serial Port
VQ
Internal Reference Voltages
Slave Mode Auto-detect
SCLK LRCK SDOUT
M0 M1
Single-Ended Analog Input
AINR
Switch-Cap ADC
High-Pass Filter
Low-Latency Digital Filters
Mode Configuration Reset
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Copyright (c) Cirrus Logic, Inc. 2006 (All Rights Reserved)
APRIL '06 DS564F1
CS5341
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 4 SPECIFIED OPERATING CONDITIONS ............................................................................................... 4 ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 4 ANALOG CHARACTERISTICS - COMMERCIAL GRADE .................................................................... 5 ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE ..................................................................... 6 DIGITAL FILTER CHARACTERISTICS ................................................................................................. 7 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 10 DIGITAL CHARACTERISTICS ............................................................................................................. 10 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................... 11 2. PIN DESCRIPTION .............................................................................................................................. 13 3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 14 4. APPLICATIONS ................................................................................................................................... 15 4.1 Single-, Double-, and Quad-Speed Modes ..................................................................................... 15 4.2 Operation as Either a Clock Master or Slave ................................................................................. 15 4.2.1 Operation as a Clock Master ................................................................................................. 16 4.2.2 Operation as a Clock Slave with Auto-Detect ....................................................................... 16 4.2.3 Master Clock ......................................................................................................................... 17 4.3 Serial Audio Interface ..................................................................................................................... 17 4.4 Power-Up Sequence ...................................................................................................................... 18 4.5 Analog Connections ....................................................................................................................... 18 4.6 Grounding and Power Supply Decoupling ...................................................................................... 18 4.7 Synchronization of Multiple Devices ............................................................................................... 18 4.8 Capacitor Size on the Reference Pin (FILT+) ................................................................................ 19 5. PARAMETER DEFINITIONS ................................................................................................................ 20 6. PACKAGE DIMENSIONS ................................................................................................................... 21 THERMAL CHARACTERISTICS .......................................................................................................... 21 7. ORDERING INFORMATION ................................................................................................................ 22 8. REVISION HISTORY ............................................................................................................................ 22
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LIST OF FIGURES
Figure 1.Single-Speed Mode Stopband Rejection ...................................................................................... 8 Figure 2.Single-Speed Mode Stopband Rejection ...................................................................................... 8 Figure 3.Single-Speed Mode Transition Band (Detail) ................................................................................ 8 Figure 4.Single-Speed Mode Passband Ripple .......................................................................................... 8 Figure 5.Double-Speed Mode Stopband Rejection ..................................................................................... 8 Figure 6.Double-Speed Mode Stopband Rejection ..................................................................................... 8 Figure 7.Double-Speed Mode Transition Band (Detail) .............................................................................. 9 Figure 8.Double-Speed Mode Passband Ripple ......................................................................................... 9 Figure 9.Quad-Speed Mode Stopband Rejection ....................................................................................... 9 Figure 10.Quad-Speed Mode Stopband Rejection ..................................................................................... 9 Figure 11.Quad-Speed Mode Transition Band (Detail) ............................................................................... 9 Figure 12.Quad-Speed Mode Passband Ripple ......................................................................................... 9 Figure 13.Master Mode, Left-Justified SAI ................................................................................................ 12 Figure 14.Slave Mode, Left-Justified SAI .................................................................................................. 12 Figure 15.Master Mode, IS SAI ................................................................................................................ 12 Figure 16.Slave Mode, IS SAI .................................................................................................................. 12 Figure 17.Typical Connection Diagram ..................................................................................................... 14 Figure 18.CS5341 Master Mode Clocking ................................................................................................ 16 Figure 19.IS Serial Audio Interface .......................................................................................................... 17 Figure 20.Left-Justified Serial Audio Interface .......................................................................................... 17 Figure 21.CS5341 Recommended Analog Input Buffer ............................................................................ 18 Figure 22.CS5341 THD+N versus Frequency .......................................................................................... 19
LIST OF TABLES
Table 1. Speed Modes and the Associated Output Sample Rates (Fs) .................................................... 15 Table 2. CS5341 Mode Control ................................................................................................................. 15 Table 3. Master Clock (MCLK) Ratios ....................................................................................................... 17 Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates ...................................... 17
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CS5341 1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and TA = 25C.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V.) Parameter
Power Supplies Analog Digital Logic Commercial Automotive
Symbol
VA VD VL TAC TAC
Min
3.1 3.1 1.7 -10 -40
Typ
(Note 1) 3.3 3.3 -
Max
5.25 5.25 5.25 70 85
Unit
V V V C C
Ambient Operating Temperature
Notes: 1. This part is specified at typical analog voltages of 3.3 V and 5.0 V. See Analog Characteristics - Commercial Grade and Analog Characteristics - Automotive Grade, below, for details.
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V, All voltages with respect to ground.) (Note 2) Parameter
DC Power Supplies: Analog Logic Digital (Note 3) (Note 4) (Note 4)
Symbol VA VL VD Iin VIN VIND
TA
Min -0.3 -0.3 -0.3 -10 GND-0.7 -0.7 -50 -65
Max +6.0 +6.0 +6.0 +10 VA+0.7 VL+0.7 +95 +150
Units V V V mA V V
C
Input Current Analog Input Voltage Digital Input Voltage Ambient Operating Temperature (Power Applied) Storage Temperature
Tstg
C
2. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 3. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SRC latch-up. 4. The maximum over/under voltage is limited by the input current.
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CS5341 ANALOG CHARACTERISTICS - COMMERCIAL GRADE
Test Conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Dynamic Performance for Commercial Grade Single-Speed Mode
Dynamic Range Total Harmonic Distortion + Noise
VA = 5 V Min
99 96
VA = 3.3 V Max
-92 -
Fs = 48 kHz
A-weighted unweighted (Note 5) -1 dB -20 dB -60 dB
Symbol
Typ
105 102 -98 -82 -42
Min
96 93 -
Typ
102 99 -95 -79 -39
Max
-89 -
Unit
dB dB dB dB dB
THD+N -
Double-Speed Mode
Dynamic Range
Fs = 96 kHz
Symbol
Min
99 96 -
Typ
105 102 99
Max
-
Min
96 93 -
Typ
102 99 96
Max
-
Unit
dB dB dB
A-weighted unweighted 40 kHz bandwidth unweighted (Note 5) -1 dB -20 dB -60 dB -1 dB THD+N
Total Harmonic Distortion + Noise
40 kHz bandwidth
-
-98 -82 -42 -95
-92 -
-
-95 -79 -39 -87
-89 -
dB dB dB dB
Quad-Speed Mode
Dynamic Range
Fs = 192 kHz
Symbol
Min
99 96 -
Typ
105 102 99
Max
-
Min
96 93 -
Typ
102 99 96
Max
-
Unit
dB dB dB
A-weighted unweighted 40 kHz bandwidth unweighted (Note 5) -1 dB -20 dB -60 dB -1 dB THD+N
Total Harmonic Distortion + Noise
40 kHz bandwidth
-
-98 -82 -42 -95
-92 -
-
-95 -79 -39 -87
-89 -
dB dB dB dB
Dynamic Performance All Modes
Interchannel Isolation
Min
-
Typ
90
Max
-
Unit
dB
DC Accuracy
Interchannel Gain Mismatch Gain Error Gain Drift -5 0.1 +5 dB % ppm/C
100
0.56*VA 25
Analog Input Characteristics
Full-Scale Input Voltage Input Impedance 0.53*VA 0.59*VA Vpp
k
5. Referred to the typical full-scale input voltage
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CS5341 ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE
Test Conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Dynamic Performance for Automotive Grade Single-Speed Mode
Dynamic Range Total Harmonic Distortion + Noise
VA = 5 V Min
97 94
VA = 3.3 V Max
-90 -
Fs = 48 kHz
A-weighted unweighted (Note 6) -1 dB -20 dB -60 dB
Symbol
Typ
105 102 -98 -82 -42
Min
94 91 -
Typ
102 99 -95 -79 -39
Max
-87 -
Unit
dB dB dB dB dB
THD+N -
Double-Speed Mode
Dynamic Range
Fs = 96 kHz
Symbol
Min
97 94 -
Typ
105 102 99
Max
-
Min
94 91 -
Typ
102 99 96
Max
-
Unit
dB dB dB
A-weighted unweighted 40 kHz bandwidth unweighted (Note 6) -1 dB -20 dB -60 dB -1 dB THD+N
Total Harmonic Distortion + Noise
40 kHz bandwidth
-
-98 -82 -42 -95
-90 -
-
-95 -79 -39 -87
-87 -
dB dB dB dB
Quad-Speed Mode
Dynamic Range
Fs = 192 kHz
Symbol
Min
97 94 -
Typ
105 102 99
Max
-
Min
94 91 -
Typ
102 99 96
Max
-
Unit
dB dB dB
A-weighted unweighted 40 kHz bandwidth unweighted (Note 6) -1 dB -20 dB -60 dB -1 dB THD+N
Total Harmonic Distortion + Noise
40 kHz bandwidth
-
-98 -82 -42 -95
-90 -
-
-95 -79 -39 -87
-87 -
dB dB dB dB
Dynamic Performance All Modes
Interchannel Isolation
Min
-
Typ
90
Max
-
Unit
dB
DC Accuracy
Interchannel Gain Mismatch Gain Error Gain Drift -10 0.1 +10 dB % ppm/C
100
0.56*VA 25
Analog Input Characteristics
Full-Scale Input Voltage Input Impedance 0.50*VA 0.62*VA Vpp
k
6. Referred to the typical full-scale input voltage
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CS5341 DIGITAL FILTER CHARACTERISTICS
Parameter Single-Speed Mode
Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) tgd (Note 7) (Note 7) tgd (Note 7) (Note 7) tgd (Note 7) (-0.1 dB) (Note 7) 0 -0.035 0.5687 70 0 -0.025 0.5604 69 0 -0.025 0.5 60 (Note 8) (Note 8) 12/Fs 9/Fs 5/Fs 1 20 10 0.4895 0.035 0.4895 0.025 0.2604 0.025 0 Fs dB Fs dB s Fs dB Fs dB s Fs dB Fs dB s Hz Hz Deg dB
Symbol
Min
Typ
Max
Unit
Double-Speed Mode
Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) (-0.1 dB)
Quad-Speed Mode
Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) (-0.1 dB)
High-Pass Filter Characteristics
Frequency Response Phase Deviation Passband Ripple -3.0 dB -0.13 dB @ 20 Hz
7. Filter characteristics scale precisely with Fs 8. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
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CS5341
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.42 0.44
Amplitude (dB)
Amplitude (dB)
0.46 0.48 0.50
0.52
0.54
0.56
0.58
0.60
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 1. Single-Speed Mode Stopband Rejection
Figure 2. Single-Speed Mode Stopband Rejection
0 -1 -2
0.10 0.08 0.06
Amplitude (dB)
Amplitude (dB)
-3 -4 -5 -6 -7 -8 -9 -10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 3. Single-Speed Mode Transition Band (Detail)
Figure 4. Single-Speed Mode Passband Ripple
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.42 0.44
Amplitude (dB)
Amplitude (dB)
0.46 0.48 0.50
0.52
0.54
0.56
0.58
0.60
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 5. Double-Speed Mode Stopband Rejection
Figure 6. Double-Speed Mode Stopband Rejection
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0 -1 -2 0.10 0.08 0.06
Amplitude (dB)
-3 -4 -5 -6 -7 -8 -9 -10 0.46 0.47 0.48 0.49 0.50 0.51 0.52
Amplitude (dB)
0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 7. Double-Speed Mode Transition Band (Detail)
Figure 8. Double-Speed Mode Passband Ripple
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
Amplitude (dB)
Frequency (norm alized to Fs)
Amplitude (dB)
Frequency (norm alized to Fs)
Figure 9. Quad-Speed Mode Stopband Rejection
Figure 10. Quad-Speed Mode Stopband Rejection
0 -1 -2 0.10 0.08 0.06
Amplitude (dB)
-3
Amplitude (dB)
0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
-4 -5 -6 -7 -8 -9 -10 0.10
0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 11. Quad-Speed Mode Transition Band (Detail)
Figure 12. Quad-Speed Mode Passband Ripple
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CS5341 DC ELECTRICAL CHARACTERISTICS
(GND = 0 V, all voltages with respect to 0 V. MCLK=12.288 MHz; Master Mode) Parameter
DC Power Supplies: Positive Analog Positive Digital Positive Logic VA = 5 V VA = 3.3 V VL,VD = 5 V VL,VD = 3.3 V Power Supply Current (Power-Down Mode) (Note 9) Power Consumption (Normal Operation) Power Supply Rejection Ratio (1 kHz) VQ Nominal Voltage Output Impedance Filt+ Nominal Voltage Output Impedance Maximum allowable DC current source/sink VA = 5 V VL,VD=5 V VL, VD, VA = 5 V VL, VD, VA = 3.3 V (Power-Down Mode) (Note 10)
Symbol
VA VD VL IA IA ID ID IA ID PSRR
Min
3.1 3.1 1.7 -
Typ
21 18.2 15 9 1.5 0.4 180 90 9.5 65 VA/2 25 VA 36 0.01
Max
5.25 5.25 5.25 25.5 22.5 18.5 10 220 107.2 -
Unit
V V V mA mA mA mA mA mA mW mW mW dB V k V k mA
Power Supply Current (Normal Operation)
9. Power-Down Mode is defined as RST = Low, with all clocks and data lines held static at a valid logic levels. 10. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection Diagram.
DIGITAL CHARACTERISTICS
Parameter
High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage at Io = 100 A Low-Level Output Voltage at Io =100 A Input Leakage Current (% of VL) (% of VL) (% of VL) (% of VL)
Symbol
VIH VIL VOH VOL Iin
Min
70% 70% -10
Typ
-
Max
30% 15% +10
Units
V V V V A
10
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CS5341 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(Logic "0" = GND = 0 V; Logic "1" = VL, CL = 20 pF) Parameter MCLK Specifications
MCLK Period tclkw 39 78 MCLK Pulse Duty Cycle 40 45 1953 60 ns ns %
Symbol
Min
Typ
Max
Unit
Master Mode
SCLK falling to LRCK Single-Speed Double-Speed Quad-Speed SCLK falling to SDOUT valid. SCLK Duty Cycle. Single-Speed Double-Speed Quad-Speed tsdo tmslr -20 -20 -8 50 50 33 20 20 8 32 ns ns ns ns % % %
Slave Mode Single-Speed (Note 11)
LRCK Duty Cycle SCLK Period SCLK Duty Cycle SDOUT valid before SCLK rising SDOUT valid after SCLK rising SCLK falling to LRCK edge tstp thld tslrd tsclkw 40 156 45 10 5 -20 50 50 60 55 20 % ns % ns ns ns
Double-Speed (Note 11)
LRCK Duty Cycle SCLK Period SCLK Duty Cycle SDOUT valid before SCLK rising SDOUT valid after SCLK rising SCLK falling to LRCK edge. tstp thld tslrd tsclkw 40 156 45 10 5 -20 40 tsclkw 78 29.7 tstp thld tslrd 10 5 -8 50 50 50 33 60 55 20 60 50 8 % ns % ns ns ns % ns % ns ns ns
Quad-Speed (Note 11)
LRCK Duty Cycle SCLK Period SCLK Duty Cycle SDOUT valid before SCLK rising SDOUT valid after SCLK rising SCLK falling to LRCK edge.
11. For a description of speed modes, please refer to Table 1 on page 15.
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CS5341
SCLK output t mslr LRCK output t sdo S DOUT MSB MSB-1
LRCK input
t slrd t sclkw
SCLK input
t stp thld
SDOUT
MSB
MSB-1
Figure 13. Master Mode, Left-Justified SAI
Figure 14. Slave Mode, Left-Justified SAI
SCLK output t mslr LRCK output t sdo S DOUT MSB
LRCK input
t slrd tsclkw
SCLK input
t stp thld
SDOUT
MSB
Figure 15. Master Mode, IS SAI
Figure 16. Slave Mode, IS SAI
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CS5341 2. PIN DESCRIPTION
M0 MCLK VL SDOUT GND VD SCLK LRCK 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 M1 FILT+ REF_GND VA AINR VQ AINL RST
Pin Name
M0 M1 MCLK VL SDOUT GND VD SCLK LRCK RST AINL AINR VQ VA FILT+
#
1 16 2 3 4 5,14 6 7 8 9 10 12 11 13 15
Pin Description
Mode Selection (Input) - Determines the operational mode of the device. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Logic Power (Input) - Positive power for the digital input/output. Serial Audio Data Output (Output) - Output for two's complement serial audio data. Ground (Input) - Ground reference. Must be connected to analog ground. Digital Power (Input) - Positive power supply for the digital section. Serial Clock (Input/Output) - Serial clock for the serial audio interface. Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. Reset (Input) - The device enters a low power mode when low. Analog Input (Input) - The full-scale analog input level is specified in the Analog Characteristics specification table. Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage. Analog Power (Input) - Positive power supply for the analog section. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
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CS5341 3. TYPICAL CONNECTION DIAGRAM
3.3V to 5V
+
1 F
0.1 F
**
0.1 F
+
1 F
1.8 V to 5V
3.3V to 5V
+
1 F
0.1 F
5.1
0.1 F
VA FILT+
1 F
*** +
VD
VL
0.1 F
REFGND +
1F 0.1 F
VQ RST M0 M1 VL or GND Power Down and Mode Settings
CS5341 A/D CONVERTER
10k
AINL Analog Input Buffer Figure 21 AINR MCLK LRCK SCLK SDOUT
*
Audio Data Processor
Timing Logic and Clock
GND
*** Capacitor value affects * Pull-up to VL for I2S Pull-down to GND for LJ low frequency distortion performance as described ** Resistor may only be in Section 4.8 used if VD is derived from VA. If used, do not drive any other logic from VD
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CS5341 4. APPLICATIONS
4.1 Single-, Double-, and Quad-Speed Modes
The CS5341 can support output sample rates from 2 kHz to 200 kHz. The proper speed mode can be determined by the desired output sample rate and the external MCLK/LRCK ratio, as shown in Table 1.
Speed Mode
Single-Speed Mode Double-Speed Mode Quad-Speed Mode
MCLK/LRCK Ratio
512x 256x 256x 128x 128x 64x*
Output Sample Rate Range (kHz)
43 - 50 2 - 50 86 - 100 50 - 100 172 - 200 100 - 200
* Quad-Speed Mode, 64x only available in Master Mode.
Table 1. Speed Modes and the Associated Output Sample Rates (Fs)
4.2
Operation as Either a Clock Master or Slave
The CS5341 supports operation as either a clock master or slave. As a clock master, the LRCK and SCLK pins are outputs with the left/right and serial clocks synchronously generated on-chip. As a clock slave, the LRCK and SCLK pins are inputs and require the left/right and serial clocks to be externally generated. The selection of clock master or slave is made via the Mode pins as shown in Table 2. M1 (Pin 16) 0 0 1 1 M0 (Pin 1) 0 1 0 1 MODE
Clock Master, Single-Speed Mode Clock Master, Double-Speed Mode Clock Master, Quad-Speed Mode Clock Slave, All Speed Modes
Table 2. CS5341 Mode Control
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CS5341
4.2.1 Operation as a Clock Master
As a clock master, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 18.
/ 256 / 128 / 64 /1 MCLK /2 1 /4 Auto-Select /2 /1 0
Single Speed Double Speed Quad Speed
00 01 10
LRCK Output (Equal to Fs)
M1
M0
Single Speed Double Speed Quad Speed
00 01 10
SCLK Output
Figure 18. CS5341 Master Mode Clocking
4.2.2
Operation as a Clock Slave with Auto-Detect
LRCK and SCLK operate as inputs in clock Slave Mode. It is recommended that the left/right clock be synchronously derived from the master clock and must be equal to Fs. It is also recommended that the serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system performance. A unique feature of the CS5341 is the automatic selection of either Single-, Double- or Quad-Speed Mode when operating as a clock slave. The auto-mode select feature negates the need to configure the Mode pins to correspond to the desired mode. The auto-mode selection feature supports all standard audio sample rates from 2 to 200 kHz. However, there are ranges of non-standard audio sample rates that are not supported when operating with a fast MCLK (512x, 256x, 128x for Single-, Double-, and Quad-Speed Modes, respectively). Please refer to Table 1 for supported sample rate ranges.
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4.2.3 Master Clock
The CS5341 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters. There is also an internal MCLK divider which is automatically activated based on the speed mode and frequency of the MCLK. Table 3 shows a listing of the external MCLK/LRCK ratios that are required. Table 4 lists some common audio output sample rates and the required MCLK frequency. Please note that not all of the listed sample rates are supported when operating with a fast MCLK (512x, 256x, 128x for Single-, Double-, and Quad-Speed Modes, respectively). Single-Speed Mode
MCLK/LRCK Ratio 256x, 512x * Quad Speed, 64x only available in Master Mode.
Table 3. Master Clock (MCLK) Ratios
Double-Speed Mode
128x, 256x
Quad-Speed Mode
64x*,128x
SAMPLE RATE (kHz)
32 44.1 48 64 88.2 96 192
MCLK (MHz)
8.192 11.2896 22.5792 12.288 24.576 8.192 11.2896 22.5792 12.288 24.576 12.288 24.576
Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates
4.3
Serial Audio Interface
The CS5341 supports both IS and Left-Justified serial audio formats. Upon start-up, the CS5341 will detect the logic level on SDOUT (pin 4). A 10 k pull-up to VL is needed to select IS format, and a 10 k pulldown to GND is needed to select Left-Justified format. Figures 19 and 20 illustrate the IS and Left-Justified audio formats. Please see Figures 13 through 16, for more information on the required timing for the two serial audio interface formats. Also see Application Note AN282 for a detailed discussion of the serial audio interface formats.
LRCK Left Channel Right Channel
SCLK
SDATA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
Figure 19. IS Serial Audio Interface
LRCK Left Channel Right Channel
SCLK
SDATA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
Figure 20. Left-Justified Serial Audio Interface
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CS5341
4.4 Power-Up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the minimum specified operating voltages to prevent power-glitch-related issues.
4.5
Analog Connections
The analog modulator samples the input at half of the MCLK frequency, or nominally 6.144 MHz. The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are multiples of the input sampling frequency (n x 6.144 MHz), where n=0,1,2,... Refer to Figure 21, which shows the suggested filter that will attenuate any noise energy at 6.144 MHz in addition to providing the optimum source impedance for the modulators. The use of capacitors that have a large voltage coefficient (such as general-purpose ceramics) must be avoided since these can degrade signal linearity.
634 VA 100 k 4.7 F A IN x 2700 pF 100 k 470 pF C 0G 91 C S 5341 A IN x
Figure 21. CS5341 Recommended Analog Input Buffer
4.6
Grounding and Power Supply Decoupling
As with any high resolution converter, achieving optimal performance from the CS5341 requires careful attention to power supply and grounding arrangements. Figure 17 shows the recommended power arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no additional devices should be powered from VD. Decoupling capacitors should be as near to the ADC as possible, with the low-value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.01 F, must be positioned to minimize the electrical path from FILT+ and REF_GND. Furthermore, all ground pins on CS5341 should be referenced to the same ground reference. The CDB5341 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
4.7
Synchronization of Multiple Devices
In systems where multiple ADCs are required, the user can achieve simultaneous sampling if the MCLK and LRCK signals are the same for all of the CS5341's in the system. If only one master clock source is needed, one solution is to place one CS5341 in Master Mode, and slave all of the other CS5341's to the one master. If multiple master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS5341 reset with the inactive (falling) edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.
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CS5341
4.8 Capacitor Size on the Reference Pin (FILT+)
The CS5341 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this decoupling capacitor will affect the low frequency distortion performance as shown in Figure 22, with larger capacitor values used to optimize low frequency distortion performance. This plot was taken using the CDB5341 evaluation platform, with the device running in Single-Speed Mode and VA=VD=VL=5 V.
1 uF
2.2 uF
3.3 uF
4.7 uF 5.6 uF 6.8 uF
10 uF
22 uF 47 uF
100 uF
Figure 22. CS5341 THD+N versus Frequency
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CS5341 5. PARAMETER DEFINITIONS
Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog input for a full-scale digital output. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
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CS5341 6. PACKAGE DIMENSIONS 16L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11 A2 A1
L
E
A
e b2 SIDE VIEW END VIEW SEATING PLANE
123
TOP VIEW
DIM A A1 A2 b D E E1 e L
MIN -0.002 0.03346 0.00748 0.193 0.248 0.169 -0.020 0
INCHES NOM -0.004 0.0354 0.0096 0.1969 0.2519 0.1732 0.026 BSC 0.024 4
MAX 0.043 0.006 0.037 0.012 0.201 0.256 0.177 -0.028 8
MIN -0.05 0.85 0.19 4.90 6.30 4.30 -0.50 0
MILLIMETERS NOM --0.90 0.245 5.00 6.40 4.40 0.65 BSC 0.60 4
NOTE MAX 1.10 0.15 0.95 0.30 5.10 6.50 4.50 -0.70 8
2,3 1 1
JEDEC #: MO-153 Controlling Dimension is Millimeters 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
THERMAL CHARACTERISTICS
Parameter
Allowable Junction Temperature Junction to Ambient Thermal Impedance
Symbol
Min
-
Typ
75
Max
135 -
Unit C C/W
JA
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CS5341 7. ORDERING INFORMATION
Description Package Pb-Free Grade Temp Range Container Bulk 105 dB, 192 kHz, Multi-Bit CS5341 16-TSSOP YES Commercial -10 to +70 C Audio A/D Converter Tape & Reel Bulk 105 dB, 192 kHz, Multi-Bit CS5341 16-TSSOP YES Automotive -40 to +85 C Audio A/D Converter Tape & Reel CDB5341 CS5341 Evaluation Board Product Order # CS5341-CZZ CS5341-CZZR CS5341-DZZ CS5341-DZZR CDB5341
8. REVISION HISTORY
Release
A1 A2 Initial Advance release Updated serial port timing specifications Change value of capacitors in analog input buffer diagram Update Sample Rate range Added Applications section on FILT+ filter capacitor Add CS5341-CZZ as part number Replace available part number CS5341-DZ with CS5341-DZZ Initial Preliminary product release Add lead-free option to ordering information Remove CS5341-CZ from Ordering Information Redefine Serial Audio Port Switching Characteristics Correct dimension "e" under Package Dimensions Update maximum current and power specifications Update Filt+ output impedance specification
Changes
PP1
PP2
F1
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com.
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. IC is a registered trademark of Philips Semiconductor.
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